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CY7C1041CV33
4-Mbit (256K x 16) Static RAM
Features
Functional Description
The CY7C1041CV33 is a high performance CMOS static RAM organized as 262,144 words by 16 bits. To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from IO pins (IO0 through IO7), is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from IO pins (IO8 through IO15) is written into the location specified on the address pins (A0 through A17). To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appear on IO0 to IO7. If Byte High Enable (BHE) is LOW, then data from memory appears on IO8 to IO15. For more information, see the Truth Table on page 9 for a complete description of Read and Write modes. The input and output pins (IO0 through IO15) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW and WE LOW). For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.
Temperature ranges Commercial: 0C to 70C Industrial: -40C to 85C Automotive-A: -40C to 85C Automotive-E: -40C to 125C Pin and function compatible with CY7C1041BV33 High speed tAA = 10 ns (Commercial, Industrial and Automotive-A) tAA = 12 ns (Automotive-E) Low active power 324 mW (max) 2.0V data retention Automatic power down when deselected TTL-compatible inputs and outputs Easy memory expansion with CE and OE features Available in Pb-free and non Pb-free 44-pin 400 Mil SOJ, 44-pin TSOP II and 48-Ball FBGA packages

Logic Block Diagram
INPUT BUFFER A0 A1 A2 A3 A4 A5 A6 A7 A8
ROW DECODER
256K x 16 RAM Array
SENSE AMPS
IO0-IO7 IO8-IO15
COLUMN DECODER
BHE WE CE OE BLE
A10 A11
A12
A14
Cypress Semiconductor Corporation Document Number: 38-05134 Rev. *I
*
198 Champion Court
A13
A16 A17
A15
A9
*
San Jose, CA 95134-1709 * 408-943-2600 Revised February 14, 2008
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CY7C1041CV33
Selection Guide
Description Maximum Access Time Maximum Operating Current Commercial Industrial Automotive-A Automotive-E Maximum CMOS Standby Current Commercial/ Industrial Automotive-A Automotive-E 10 10 15 -10 10 90 100 100 120 10 10 -12 12 85 95 -15 15 80 90 -20 20 75 85 85 90 10 10 15 Unit ns mA mA mA mA mA mA mA
Pin Configuration
Figure 1. 44-Pin SOJ/TSOP II (Top View) [1] Figure 2. 48-Ball FBGA Pinout (Top View) [1]
A0 A1 A2 A3 A4 CE IO0 IO1 IO2 IO3 VCC VSS IO4 IO5 IO6 IO7 WE A5 A6 A7 A8 A9
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
A17 A16 A15 OE BHE BLE IO15 IO14 IO13 IO12 VSS VCC IO11 IO10 IO9 IO8 NC A14 A13 A12 A11 A10
1 BLE IO0 IO1 VSS VCC IO6 IO7 NC
2 OE BHE IO2 IO3 IO4 IO5 NC A8
3 A0 A3 A5 A17 NC A14 A12 A9
4 A1 A4 A6 A7 A16 A15 A13 A10
5 A2 CE IO10
6 NC IO8 IO9 A B C D E F G H
IO11 VCC IO12 IO13 WE A11 VSS IO14 IO15 NC
Note 1. NC pins are not connected on the die.
Document Number: 38-05134 Rev. *I
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CY7C1041CV33
Pin Definitions
Pin Name A0-A17 SOJ, TSOP Pin Number 1-5, 18-27, 42-44 BGA Pin Number A3, A4, A5, B3, B4, C3, C4, D4, H2, H3, H4, H5, G3, G4, F3, F4, E4, D3 IO Type Input Description Address Inputs. Used to select one of the address locations.
IO0-IO15
7-10,13-16, B1, C1, C2, D2, Input or Output Bidirectional Data IO lines. Used as input or output lines depending 29-32, 35-38 E2, F2, F1, G1, on operation. B6, C6, C5, D5, E5, F5, F6, G6 28 17 6 40, 39 41 A6, E3, G2, H1, H6 G5 B5 B2, A1 A2 No Connect Input or Control Input or Control Input or Control Input or Control No Connects. Not connected to the die. Write Enable Input, Active LOW. When selected LOW, a write is conducted. When deselected HIGH, a read is conducted. Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. Byte Write Select Inputs, Active LOW. BHE controls IO16 - IO9, BLE controls IO8 - IO1. Output Enable, Active LOW. Controls the direction of the IO pins. When LOW, the IO pins are allowed to behave as outputs. When deasserted HIGH, the IO pins are tri-stated and act as input data pins. Ground for the Device. Connected to ground of the system.
NC WE CE BHE, BLE OE
VSS VCC
12, 34 11, 33
D1, E6 D6, E1
Ground
Power Supply Power Supply Inputs to the Device.
Document Number: 38-05134 Rev. *I
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CY7C1041CV33
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied ............................................ -55C to +125C Supply Voltage on VCC Relative to GND[2] .....-0.5V to +4.6V DC Voltage Applied to Outputs in High Z State[2] ...................................... -0.5V to VCC+0.5V DC Input Voltage[2] .................................. -0.5V to VCC+0.5V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage............................................ >2001V (MIL-STD-883, Method 3015) Latch Up Current ..................................................... >200 mA
Operating Range
Range Commercial Industrial Automotive-A Automotive -E Ambient Temperature (TA) 0C to +70C -40C to +85C -40C to +85C -40C to +125C VCC 3.3V 10%
Electrical Characteristics
Over the Operating Range Parameter VOH VOL VIH VIL [2] IIX Description Test Conditions -10 Min 2.4 0.4 2.0 -0.3 GND < VI < VCC Com'l/Ind'l Auto-A Auto-E IOZ Output Leakage Current GND < VOUT < VCC, Com'l/Ind'l Output disabled Auto-A Auto-E ICC VCC Operating Supply Current VCC = Max, f = fMAX = 1/tRC Com'l Ind'l Auto-A Auto-E ISB1 Automatic CE Power Max VCC, Down Current --TTL CE > VIH VIN > VIH or Inputs VIN < VIL, f = fMAX Com'l/Ind'l Auto-A Auto-E 10 10 15 40 40 45 10 10 90 100 100 120 40 40 -1 -1 +1 +1 -20 +20 85 95 80 90 -1 -1 VCC + 0.3 0.8 +1 +1 -20 -1 +20 +1 -1 +1 2.0 -0.3 -1 Max 2.4 0.4 VCC + 0.3 0.8 +1 2.0 -0.3 -1 -12 Min Max 2.4 0.4 VCC + 0.3 0.8 +1 2.0 -0.3 -1 -1 -20 -1 -1 -20 -15 Min Max 2.4 0.4 VCC + 0.3 0.8 +1 +1 +20 +1 +1 +20 75 85 85 90 40 40 45 10 10 15 mA mA mA A -20 Min Max Unit V V V V A
Output HIGH Voltage VCC = Min, IOH = -4.0 mA Output LOW Voltage VCC = Min, IOL = 8.0 mA Input HIGH Voltage Input LOW Voltage Input Leakage Current
ISB2
Automatic CE Power Max VCC, Com'l/Ind'l Down Current -- CE > VCC - 0.3V, Auto-A CMOS Inputs VIN > VCC - 0.3V, or VIN < 0.3V, f = 0 Auto-E
Note 2. VIL (min) = -2.0V and VIH(max) = VCC + 0.5V for pulse durations of less than 20 ns.
Document Number: 38-05134 Rev. *I
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CY7C1041CV33
Capacitance
Tested initially and after any design or process changes that may affect these parameters. Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V Max 8 8 Unit pF pF
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters. Parameter Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51 SOJ 25.99 18.8 TSOP II 42.96 10.75 FBGA 38.15 9.15 Unit C/W C/W
JA JC
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms [3]
10-ns devices: OUTPUT 50 * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 1.5V 12-, 15-, 20-ns devices: Z = 50 3.3V
R 317
30 pF*
OUTPUT
30 pF*
R2 351
(a)
(b)
High-Z characteristics: 3.0V GND ALL INPUT PULSES 90% 10% 90% 10% R 317 3.3V OUTPUT 5 pF R2 351
Rise Time: 1 V/ns
(c)
Fall Time: 1 V/ns
(d)
Note 3. AC characteristics (except High-Z) for 10-ns parts are tested using the load conditions shown in Figure (a). All other speeds are tested using the Thevenin load shown in Figure (b). High-Z characteristics are tested for all speeds using the test load shown in Figure (d).
Document Number: 38-05134 Rev. *I
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CY7C1041CV33
Switching Characteristics
Over the Operating Range [4] Parameter Read Cycle tpower[5] tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write Cycle tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW VCC(Typical) to the First Access Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z CE LOW to Low Z
[6]
Description
-10 Min 100 10 10 3 10 5 0 5 3 5 0 10 0 3 0 3 Max
-12 Min 100 12 12 3 12 6 7 0 6 3 6 0 12 6 7 0 6 6 12 8 8 0 0 8 6 0 3 5 6 8 10 15 10 10 0 0 10 7 0 3 0 Max
-15 Min 100 15 15 3 15 7 0 7 3 7 0 15 7 0 7 20 10 10 0 0 10 8 0 3 7 10 Max
-20 Min 100 20 20 20 8 8 Max
Unit
s ns ns ns ns ns ns 8 8 20 8 8 ns 8 ns ns ns ns ns ns ns ns ns ns 8 ns ns ns ns ns ns ns ns
Comm'l/Ind'l/Auto-A Auto-E
OE HIGH to High Z[6, 7]
[6] [6, 7]
CE HIGH to High Z
CE LOW to Power Up CE HIGH to Power Down Byte Enable to Data Valid Byte Enable to Low Z Byte Disable to High Z
[8, 9]
Comm'l/Ind'l/Auto-A Auto-E 0
5
Write Cycle Time CE LOW to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start WE Pulse Width Data Setup to Write End Data Hold from Write End WE HIGH to Low WE LOW to High Z[6] Z[6, 7]
10 7 7 0 0 7 5 0 3 7
Byte Enable to End of Write
Notes 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and input pulse levels of 0 to 3.0V. 5. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed. 6. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 7. tHZOE, tHZCE, tHZBE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads and Waveforms on page 5. Transition is measured 500 mV from steady state voltage. 8. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW, and BHE/BLE LOW. CE, WE, and BHE/BLE must be LOW to initiate a write. The transition of these signals terminate the write. The input data setup and hold timing is referenced to the leading edge of the signal that terminates the write. 9. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document Number: 38-05134 Rev. *I
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CY7C1041CV33
Switching Waveforms
Figure 4. Read Cycle No. 1 (Address Transition Controlled)[10, 11]
tRC RC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
Figure 5. Read Cycle No. 2 (OE Controlled)[11, 12]
ADDRESS tRC CE tACE OE tDOE BHE, BLE tLZOE tDBE tLZBE DATA OUT VCC SUPPLY CURRENT HIGH IMPEDANCE tLZCE tPU 50% tHZCE tHZBE DATA VALID tPD 50% ICC ISB tHZOE
HIGH IMPEDANCE
Notes 10. Device is continuously selected. OE, CE, BHE, and/or BLE = VIL. 11. WE is HIGH for read cycle. 12. Address valid prior to or coincident with CE transition LOW.
Document Number: 38-05134 Rev. *I
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CY7C1041CV33
Switching Waveforms
(continued) Figure 6. Write Cycle No. 1 (CE Controlled)[13, 14]
tWC ADDRESS
tSA CE tAW
tSCE
tHA tPWE
WE tBW BHE, BLE tSD DATA IO tHD
Figure 7. Write Cycle No. 2 (BLE or BHE Controlled)
tWC ADDRESS
tSA BHE, BLE
tBW
tAW tPWE WE tSCE CE tSD DATA IO tHD
tHA
Notes 13. Data IO is high impedance if OE, BHE, and/or BLE = VIH. 14. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
Document Number: 38-05134 Rev. *I
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CY7C1041CV33
Switching Waveforms
(continued) Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW)
tWC ADDRESS
tSCE CE tAW tSA WE tBW BHE, BLE tPWE
tHA
tHZWE DATA IO
tSD
tHD
tLZWE
Truth Table
CE H L OE X L WE X H BLE X L L H L X L L L H L L H X H X X H BHE X L H L L H L X H IO0 - IO7 IO8 - IO15 High Z Data Out Data Out High Z Data In Data In High Z High Z High Z High Z Data Out High Z Data Out Data In High Z Data In High Z High Z Mode Power Down Read - All Bits Read - Lower Bits Only Read - Upper Bits Only Write - All Bits Write - Lower Bits Only Write - Upper Bits Only Selected, Outputs Disabled Selected, Outputs Disabled Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Power Standby (ISB)
Document Number: 38-05134 Rev. *I
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CY7C1041CV33
Ordering Information
Speed (ns) 10 Ordering Code CY7C1041CV33-10BAXC CY7C1041CV33-10VC CY7C1041CV33-10VXC CY7C1041CV33-10ZXC CY7C1041CV33-10BAI CY7C1041CV33-10BAXI CY7C1041CV33-10ZI CY7C1041CV33-10ZXI CY7C1041CV33-10BAXA CY7C1041CV33-10ZSXA 12 CY7C1041CV33-12VXC CY7C1041CV33-12ZXC CY7C1041CV33-12ZI CY7C1041CV33-12ZXI CY7C1041CV33-12BAXE CY7C1041CV33-12ZSXE 15 CY7C1041CV33-15ZXC CY7C1041CV33-15VI CY7C1041CV33-15VXI CY7C1041CV33-15ZI CY7C1041CV33-15ZXI 20 CY7C1041CV33-20ZC CY7C1041CV33-20ZSXA CY7C1041CV33-20VE CY7C1041CV33-20VXE CY7C1041CV33-20ZE CY7C1041CV33-20ZSXE Package Diagram Package Type Operating Range Commercial
51-85106 48-ball Fine Pitch BGA (Pb-Free) 51-85082 44-pin (400-mil) Molded SOJ 44-pin (400-mil) Molded SOJ (Pb-Free) 51-85087 44-pin TSOP II (Pb-Free) 51-85106 48-ball Fine Pitch BGA 48-ball Fine Pitch BGA (Pb-Free) 51-85087 44-pin TSOP II 44-pin TSOP II (Pb-Free) 51-85106 48-ball Fine Pitch BGA (Pb-Free) 51-85087 44-pin TSOP II (Pb-Free) 51-85082 44-pin (400-mil) Molded SOJ (Pb-Free) 51-85087 44-pin TSOP II (Pb-Free) 51-85087 44-pin TSOP II 44-pin TSOP II (Pb-Free) 51-85106 48-ball Fine Pitch BGA (Pb-Free) 51-85087 44-pin TSOP II (Pb-Free) 51-85087 44-pin TSOP II (Pb-Free) 51-85082 44-pin (400-mil) Molded SOJ 44-pin (400-mil) Molded SOJ (Pb-Free) 51-85087 44-pin TSOP II 44-pin TSOP II (Pb-Free) 51-85087 44-pin TSOP II 51-85087 44-pin TSOP II (Pb-Free) 51-85082 44-pin (400-mil) Molded SOJ 44-pin (400-mil) Molded SOJ (Pb-Free) 51-85087 44-pin TSOP II 44-pin TSOP II (Pb-Free)
Industrial
Automotive-A Commercial Industrial Automotive-E Commercial Industrial
Commercial Automotive-A Automotive-E
Please contact your local Cypress sales representative for availability of these parts
Document Number: 38-05134 Rev. *I
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CY7C1041CV33
Package Diagrams
Figure 9. 44-Pin (400 Mil) Molded SOJ, 51-85082
51-85082-*B
Document Number: 38-05134 Rev. *I
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CY7C1041CV33
Package Diagrams
(continued) Figure 10. 44-Pin Thin Small Outline Package Type II, 51-85087
51-85087-*A
Document Number: 38-05134 Rev. *I
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CY7C1041CV33
Package Diagrams
(continued) Figure 11. 48-Ball FBGA (7 x 8.5 x 1.2 mm), 51-85106
TOP VIEW BOTTOM VIEW
A1 CORNER O0.05 M C A1 CORNER O0.25 M C A B O0.300.05(48X) 1 2 3 4 5 6 6 5 4 3 2 1
A B C 0.75 8.500.10 8.500.10 5.25 D E F G H
A B C D E 2.625 F G H
A B 7.000.10
A
1.875 0.75 3.75 B 7.000.10
0.530.05
0.25 C
0.210.05
0.15(4X) 0.15 C 1.20 MAX.
SEATING PLANE 0.36 C
51-85106-*E
Document Number: 38-05134 Rev. *I
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CY7C1041CV33
Document History Page
Document Title: CY7C1041CV33, 4-Mbit (256K x 16) Static RAM Document Number: 38-05134 REV. ** *A *B *C *D *E *F *G ECN NO. 109513 112440 112859 116477 119797 262949 361795 435387 Issue Date 12/13/01 12/20/01 03/25/02 09/16/02 10/21/02 See ECN See ECN See ECN Orig. of Change HGK BSS DFP CEA DFP RKF SYT NXR New Data Sheet Updated 51-85106 from revision *A to *C Added CY7C1042CV33 in BGA package Removed 1042 BGA option pin ACC Final Data Sheet Add applications foot note to data sheet Added 20-ns speed bin 1) Added Lead (Pb)-Free parts in the Ordering info (Page #9) 2) Added Automotive Specs to Datasheet Added Pb-Free offerings in the Ordering Information Removed -8 Speed bin from Product offering. Corrected typo in description for BHE/BLE in pin definitions table on Page# 3 corrected their Pin name from OE2 to OE. Included the Maximum Ratings for Static Discharge Voltage and Latch up Current. Changed the description of IIX current from Input Load Current to Input Leakage Current Added note# 4 on page# 4 Updated the Ordering Information table Added Automotive-A Operating Range Changed tpower value from 1 s to 100 s Updated Ordering Information table Description of Change
*H
499153
See ECN
NXR
*I
2104110 See ECN
VKN/AESA Added Automotive-E specs for 12 ns speed Updated Ordering Information table
(c) Cypress Semiconductor Corporation, 2001-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05134 Rev. *I
Revised February 14, 2008
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